Digital Logic View
Real-time Oscilloscope
50ms/div
CLK (Clock)
D (Input)
Q (Output)
D
0.00V
> CLK
0.00V
Q
0.00V
D-FlipFlop
渲染模式 (Render Mode)
10 %
0.57 Hz
工程规范
- Logic 1 Input: 1.0V - 2.0V
- Logic 0 Input: 0.0V - 0.6V
- Unstable Zone: 0.6V - 1.0V
- Voltage Range: -0.5V - 2.5V